Cross Capacitance Noise
Noise is any deviation from a preferred or ideal signal. Applied noise voltages generate undesired voltages or currents (i.e., noise) into a node which affect an otherwise preferred or ideal signal. Multiple noise sources exist within a semiconductor IC (such as AC ripple on the power rails or thermal noise from resistive elements). Another form of noise, referred to as cross capacitance noise (referred to also as cross coupling noise or interconnect noise), occurs where neighboring signal traces are the noise source. Semiconductor ICs employ metal traces (also referred to as interconnects or interconnect traces) in order to electrically connect transistors. FIG. 1a shows a section of two neighboring metal traces 101a, 102a. Typically, the metal traces 101a, 102a are separated and surrounded by dielectric material(s) (not shown).
The combination of a dielectric sandwiched between two conducting traces forms a cross capacitor between the two traces. Thus, simply placing two interconnect traces 101a, 102a near each other forms a cross capacitor. The interconnect traces 110a, 102a may therefore be modeled as lumped elements 101b, 102b as shown in FIG. 1b. That is, a single length of neighboring traces may be viewed as sharing a pair of cross capacitances 108, 109 each having one half the total capacitance between the particular trace length. Each trace 101b, 102b also has an associated series resistance 110, 111. The model of FIG. 1b is typical of models used to predict circuit performance.
Capacitances are generally viewed as short circuits for AC signals. Thus a sudden time varying signal on a trace (e.g., time varying signal 112 on trace 101b) typically causes noise current 113 to travel from the trace 101b to the neighboring trace 102b. This noise current 113, in turn, causes a voltage perturbation 114 on the neighboring trace 102b. The voltage perturbation 114, when added to any signal on the neighboring trace 102b is typically referred to as cross capacitance noise.
As device size continues to shrink (resulting in higher and higher levels of metallization) cross capacitance problems are becoming more severe. The wafer substrate in which devices are embedded is usually grounded so the wafer substrate may be seen as a large ground plane beneath the various pairs of cross-coupled traces. This plane tends to absorb electrical flux lines emanating from the interconnect traces which decrease the cross-capacitance noise. The relationship between the interconnect traces and the grounded wafer (or to signals on other layers) may be modeled as substrate capacitances 115a, b, 116a, b. 
However, the beneficial effect of the grounded wafer is diminished at higher and higher metallization levels simply because of the increased height of the metal traces above the wafer. Thus, with higher levels of metallization (necessary to interconnect the expanding number of devices per die), the industry is experiencing more severe cross capacitance noise problems.
Circuit Modeling
Due to the expense associated with manufacturing semiconductor chips and the competitive nature of the marketplace, it is desirable to have chips yielding (i.e., the manufacture of working chips suitable for customer shipment) with the fewest development process runs possible. In order to achieve this, chip designs are typically simulated by a computing system prior to fabrication. Design defects are discovered during the simulation and the design is fixed accordingly. The time and expense saved simulating chip designs, as compared to the alternative approach of making the chip and debugging its design defects, is considerable.
Given the above described worsening of cross-capacitance noise, it is desirable to simulate its effects. However, a discussed, the noise sources associated with cross capacitance noise are neighboring signals and trace geometries. Given the highly complex relationship (in terms of timing, strength, distances, etc.) between the various signals running over traces, the various geometries between neighboring traces as well as the sheer number of signals and traces, it is extremely cumbersome to completely model these effects.
Specifically, use of SPICE modeling techniques in combination with lumped element models (such as that shown in FIG. 1b) requires too much time to simulate. Each trace bend, branch or via creates a new lumped element that must be added to the trace model. A single trace is modeled as a complicated string of lumped elements, each requiring dedicated attention during the simulation. Furthermore, SPICE modeling is an iterative process meaning each of the multiple lumped elements per trace must receive dedicated attention a plurality of times before the simulation is complete. Given the vast number of traces existing within a semiconductor IC, it is simply too inefficient to simulate cross capacitance noise in this manner.